Low Power Techniques for High Speed FPGA

The motive of this work is to design on chip efficient low power techniques using VHDL coding. Serial links in network on chip provide many advantages in terms of crosstalk, skew, area cost, clock synchronization, and wiring difficulty when compared to multi-bit parallel data transmission. The proposed a novel coding technique reduces the number of transitions and hence reduces transmission energy on the serial wire. Also low power consumption is achieved by using the mux-tree based round robin scheduler. A scheduler (or arbiter) is needed when more than two input packets from different input ports are destined for the same output port at the same time.